To transmit and receive data over any network successfully, a protocol is required to manage the flow. High-level Data Link Control (HDLC) protocol is defined in Layer 2 of OSI model and is one of the most commonly used layer 2 protocols. HDLC supports both full-duplex and halfduplex data transfer. In addition, it offers error control and flow control. Using a modified MT8952B controller design, the current research presents a new method for implementing an ultra high bit rate HDLC Controller that is compatible with ST-BUS format using Xilinx Virtex FPGA as the target technology using VHDL for implementation. The HDLC Transceiver is used to transmit and receive the HDLC frames. Implementing the HDLC protocol transceiver in FPGA offers the flexibility, upgradeability and customization benefits of programmable logic and also reduces the total cost of every project which involves HDLC protocol controllers.

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