IEICE Transactions on Fundamentals of Electronics, Communications and Computer Sciences , ( ISI ), Volume (E92-A), No (12), Year (2009-12) , Pages (3182-3192)

Title : ( Rapid Design Space Exploration of a Reconfigurable Instruction-Set Processor )

Authors: Farhad Mehdipour , Hamid Noori , Koji Inoue , Kazuaki Murakami ,

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Abstract

Multitude parameters in the design process of a reconfigurable instruction-set processor (RISP) may lead to a large design space and remarkable complexity. Quantitative design approach uses the data collected from applications to satisfy design constraints and optimize the design goals while considering the applications characteristics; however it highly depends on designer observations and analyses. Exploring design space can be considered as an effective technique to find a proper balance among various design parameters. Indeed, this approach would be computationally expensive when the performance evaluation of the design points is accomplished based on the synthesis-and-simulation technique. A combined analytical and simulation-based model (CAnSO) is proposed and validated for performance evaluation of a typical RISP. The proposed model consists of an analytical core that incorporates statistics collected from cycle-accurate simulation to make a reasonable evaluation and provide a valuable insight. CAnSO has clear speed advantages and therefore it can be used for easing a cumbersome design space exploration of a reconfigurable RISP processor and quick performance evaluation of slightly modified architectures.

Keywords

, reconfigurable instruction, set processor