Title : ( A low-power fast tag comparator by modifying charging scheme of widefan-indynamic OR gates )
Authors: Mahshid Nasserian , mohammad kafi kangi , Mohammad Maymandi Nejad , Farshad Moradi ,
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Abstract
In thispaper,anewchargingschemeforreducingthepowerconsumptionofdynamiccircuitsispre- sented. Theproposedtechniqueissuitableforlargefan-ingateswherethedynamicnodedischarges frequently.Simulationresultsdemonstratethattheproposedmethodisefficiently controllingthe internal voltageswingandhencedecreasingthepowerconsumptionofthewidefan-in OR gate without sacrificing othercircuitparameterssuchasgatespeed,areaornoiseimmunity.Thepower-delayproduct of asimulated8-input OR gate isreducedby46%,comparedtoitsconventionaldynamiccounterpartin the 90nmCMOStechnology.Anotherimportantbenefit oftheproposedapproachis99Xreductionin powerdissipationofthegateloadbylimitingitsswitchingactivity.Furthermore,thedelayofthepro- posed circuitexperiencesonly0.94%variationover10% fluctuation inthethresholdvoltagesofall transistorsfora32-bit OR gate. Usingtheproposedtechnique,a40-bittagcomparatorissimulatedat 1 GHzclockfrequency.Thepowerconsumptionofthedesignedcircuitisaslowas1.987 mW/MHz, while the delayandunitynoisegain(UNG)ofthecircuitare244psand499mV,respectively.
Keywords
, Dynamic logic, Power-delayproduct, Reducedpower, Wide fan-in
@article{paperid:1049976,
author = {Nasserian, Mahshid and Kafi Kangi, Mohammad and Maymandi Nejad, Mohammad and Farshad Moradi},
title = {A low-power fast tag comparator by modifying charging scheme of widefan-indynamic OR gates},
journal = {Integration, the VLSI Journal},
year = {2015},
volume = {52},
month = {September},
issn = {0167-9260},
pages = {129--141},
numpages = {12},
keywords = {Dynamic logic; Power-delayproduct; Reducedpower; Wide fan-in},
}
%0 Journal Article
%T A low-power fast tag comparator by modifying charging scheme of widefan-indynamic OR gates
%A Nasserian, Mahshid
%A Kafi Kangi, Mohammad
%A Maymandi Nejad, Mohammad
%A Farshad Moradi
%J Integration, the VLSI Journal
%@ 0167-9260
%D 2015
