A novel signal-specific power-efficient analog-to- digital converter (ADC) is proposed for sensor-interface applications. Instead of digitizing each analog sample independently, the proposed ADC determines the digital code corresponding to each new input sample by digitizing the difference of two consecutive samples. Therefore, for the applications with low-varying input signals, such as image sensors and ECG readouts, which the difference of two consecutive samples is much smaller than the ADC full-scale range for the majority of the input samples, the power consumption of the capacitive digital-to-analog converter (DAC), the comparator, and the digital circuits of the proposed ADC is saved due to reducing the ADC activity. The prototype was fabricated using a 0.18-μm CMOS technology. Measurement results of 1-V, 8-bit, 20-kS/s ADC confirm that for a 10-kHz input sine wave, the effective number of bits is 7 while the power consumption of the entire ADC is 1.12 μW. However, for the same sampling rate, the power consumption is only 106 nW for a low-varying 100-Hz input sine-wave.

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