SRAM-based FPGAs have found many applications in modern computer systems. In these systems, high-performance computing applications are executed as task graphs in which reliability and performance are crucial constraints. In this paper, an exact method is presented to efficiently optimize the reliability and performance of synchronous task graphs running on SRAM-based FPGAs in harsh environments. Solving this optimization problem leads to the generation of a true Pareto set of Fault Tolerance (FT) techniques. Each solution of this set determines FT techniques of the tasks and leads to specific reliability and makespan. Thus, this solution set trades off between reliability and makespan, and one of the solutions that best meets system requirements can be applied to the running tasks to optimize the reliability and performance. The proposed technique is novel as it obtains the true Pareto set of FT techniques of the whole task graph by partitioning the task graph into its segments, optimizing different segments separately, and joining the obtained solutions. This partitioning strategy leads to reduce the computation time significantly. In this paper, it is mathematically proved that the proposed partitioning strategy generates global optima from the local ones without losing any optimal solutions. The experiments show that the proposed technique improves the MTTF of real-world and random task graphs by 46.30% on average without any negative effects on the performance. Then, the efficiency of the computation time of the proposed technique is demonstrated by conducting several experiments on small-, medium-, and large-size synchronous task graphs and comparing the results with other exact and evolutionary optimization methods. Finally, supplementary experiments in dynamic environments show that the proposed technique outperforms adaptive state-of-the-art FT techniques in terms of reliability and makespan improvement.

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