Title : ( A Low Leakage Power Adder Structure for Nano-Scale CMOS )
Authors: Seyed Saied Hosseini Khayat , - - ,
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Abstract
A low leakage power 1-bit full-adder circuit suitable for implementation in deep submicron CMOS (nano-scale CMOS) technologies is proposed. In this circuit, two adder subcomponents have been designed for reduced static leakage current. HSPICE simulations in 90nm, 65nm and 45nm PTM (Predictive Technology Model) technologies show great improvements of the proposed adder with respect to other structures in term of static power consumption.
Keywords
, Adder Modules, Deep Submicron Technology, Static Power Consumption
@article{paperid:1009328,
author = {Hosseini Khayat, Seyed Saied and -, -},
title = {A Low Leakage Power Adder Structure for Nano-Scale CMOS},
journal = {International Review on Modelling and Simulations},
year = {2008},
volume = {1},
number = {2},
month = {December},
issn = {1974-9821},
pages = {281--284},
numpages = {3},
keywords = {Adder Modules; Deep Submicron Technology; Static Power Consumption},
}
%0 Journal Article
%T A Low Leakage Power Adder Structure for Nano-Scale CMOS
%A Hosseini Khayat, Seyed Saied
%A -, -
%J International Review on Modelling and Simulations
%@ 1974-9821
%D 2008
