Title : ( Power-Delay Efficient Overlap-Based Charge-Sharing Free Pseudo-Dynamic D Flip-Flops )
Authors: Omid Sarbishei , Mohammad Maymandi Nejad ,
Full TextAbstract
Clock overlap is an important issue in the design of sequential circuits and is typically avoided. In this paper we present a new power-efficient edge-triggered D flipflop in which we have benefited from the overlap period of the clock signal. The design procedure of the proposed D flip-flop is presented. The performance of the flip-flop is compared with several state of the art flip-flops in a shift register and a pipeline adder in 0.18µm CMOS technology. The proposed flip-flop has the lowest power-delay-product and consumes less area compared to others.
Keywords
, Edge-triggered D flip-flops, dynamic CMOS circuits, charge-sharing, clock overlap, power-delay product
@inproceedings{paperid:1011569,
author = {Sarbishei, Omid and Maymandi Nejad, Mohammad},
title = {Power-Delay Efficient Overlap-Based Charge-Sharing Free Pseudo-Dynamic D Flip-Flops},
booktitle = {IEEE International Symposium on Circuits and Systems-ISCAS 2007},
year = {2007},
location = {USA},
keywords = {Edge-triggered D flip-flops; dynamic CMOS circuits; charge-sharing; clock overlap; power-delay product},
}
%0 Conference Proceedings
%T Power-Delay Efficient Overlap-Based Charge-Sharing Free Pseudo-Dynamic D Flip-Flops
%A Sarbishei, Omid
%A Maymandi Nejad, Mohammad
%J IEEE International Symposium on Circuits and Systems-ISCAS 2007
%D 2007
