This paper reports on the design of an IPv4 prefix lookup engine that supports 166 million lookups per second, and an estimated 850k prefix entries. It also supports dynamic table update operations that can be issued from an external controller. The design employs a prefix search algorithm that is fine-tuned for hardware implementation. It takes advantage of pipelining and utilizes one FPGA chip and seven ZBT® SRAM chips. We have implemented this engine as an HDL core in Verilog.

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