In this paper a new architecture for successive approximation analog-to-digital converters (SAR-ADCs) using generalized non-binary search algorithm is proposed to reduce the complexity and the power consumption overhead of the digital circuitry. The proposed structure is based on the split capacitive array DAC with a simple switching logic as compared to the conventional non-binary SAR-ADC architecture. Simulation results of an 8-bit 10-step 100 kS/s converter show the efficiency of the proposed structure.

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