This paper focuses on the extraction of drain/source resistance and effective channel length (Leff) of the silicon MOSFET in the linear drain current region. Leff is expressed as a function of drain/source resistance, drain current, threshold voltage, drain voltage, and body-effect coefficient. Using this definition, an additional component of drain/source resistance in the linear drain current region, inversion charge reduction resistance (RDQ), is introduced which results from the influence of drain/source resistors, internal source/body voltage and drain voltage on the total inversion charge. Finally, a new method for extraction of the drain/source resistance is developed. In this method several parameters that have impact on device behavior are considered. The parameters include gate voltage dependency, short channel effects, and poly gate length dependency. The results presented here are not only very useful for accurate device modeling and characterization, but are also vital to better understanding of the device physics. Furthermore, they can describe shortcomings of the other methods which use devices of different gate lengths. The extracted linear model provides less than 1.07% and 3.3% average absolute error and maximum error, respectively, for all seven devices under test over the gate voltage range of 0.75–2 V.

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