Title : ( A Fully Digital Front-End Architecture for ECG Acquisition System With 0.5 V Supply )
Authors: M. Zare , Mohammad Maymandi Nejad ,
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Abstract
This paper presents a new power-efficient electrocardiogram acquisition system that uses a fully digital architecture to reduce the power consumption and chip area. The proposed architecture is compatible with digital CMOS technology and is capable of operating with a low supply voltage of 0.5 V. In this architecture, no analog block, e.g., low-noise amplifier (LNA), and filters, and no passive elements, such as ac coupling capacitors, are used. A moving average voltage-totime converter is used, which behaves instead of the LNA and antialiasing filter. A digital feedback loop is employed to cancel the impact of the dc offset on the circuit, which eliminates the need for coupling capacitors. The circuit is implemented in 0.18-um CMOS process. The simulation results show that the front-end circuit consumes 274 nW of power.
Keywords
, Antialiasing, area efficient, digital integrated circuit (IC), electrocardiogram (ECG), low power, moving average filtering, offset cancellation, sensor interface
@article{paperid:1052790,
author = {M. Zare and Maymandi Nejad, Mohammad},
title = {A Fully Digital Front-End Architecture for ECG Acquisition System With 0.5 V Supply},
journal = {IEEE Transactions on Very Large Scale Integration (VLSI) Systems},
year = {2016},
volume = {24},
number = {1},
month = {January},
issn = {1063-8210},
pages = {256--265},
numpages = {9},
keywords = {Antialiasing; area efficient; digital integrated circuit (IC); electrocardiogram (ECG); low power; moving average filtering; offset cancellation; sensor interface},
}
%0 Journal Article
%T A Fully Digital Front-End Architecture for ECG Acquisition System With 0.5 V Supply
%A M. Zare
%A Maymandi Nejad, Mohammad
%J IEEE Transactions on Very Large Scale Integration (VLSI) Systems
%@ 1063-8210
%D 2016
