In this paper, a power amplifier implemented with a common-drain structure is introduced. With proper input matching, this structure is shown to provide a reasonable power gain and superior linearity and efficiency in comparison to other low-power topologies. This is shown to be due to the low dependency of the power gain to the transistor transconductance and the low-voltage variations across the gate-source capacitance. This power amplifier is suitable for low-power and short-range applications such as Bluetooth Low Energy (BLE). Based on the calculated S-parameters, the operation frequency of this amplifier and its design trade-offs are presented, along with a comparison with competitive topologies. The design is simulated in a 0.13 um CMOS technology, operates with a 1.2 V supply, and provides a power gain of 8.5 dB with a DC power consumption of 3.6 mW. The input 1-dB compression point is 2.2 dBm, yielding a power added efficiency of 43%.

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