Title : ( A 5.3-9.3 fJ/Conversion-Step 4-32 MS/s 10 bit Asynchronous SAR ADC with Optimized DAC Timing Strategy in 0.13 μm CMOS )
Authors: mohsen dashtbayazi , Mohammad Taherzadeh-Sani , Samaneh Babayan , Ehsan Rahiminejad ,
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Abstract
In this paper, a low power SAR Analog to Digital Converter (ADC) with a resolution of 10 bits and a sampling rate of 4 to 32 MS/s is proposed. It utilizes an asynchronous process with an optimized D/A timing strategy to increase its sampling frequency. This ADC is simulated in a 130-nm CMOS technology with two power supplies of 0.6 V and 1.2 V. It achieves an ENOB greater than 9.3 bits for its full sampling-rate range (4 to 32 MS/s) with an FOM = 5.3 to 9.3 fJ/conv.-step.
Keywords
Analog to digital converter; asynchronous process; power efficiency; asynchronous clock generator circuit; low power designs.
@article{paperid:1058621,
author = {Dashtbayazi, Mohsen and Taherzadeh-Sani, Mohammad and Babayan, Samaneh and Rahiminejad, Ehsan},
title = {A 5.3-9.3 fJ/Conversion-Step 4-32 MS/s 10 bit Asynchronous SAR ADC with Optimized DAC Timing Strategy in 0.13 μm CMOS},
journal = {Journal of Electrical Systems and Signals},
year = {2014},
volume = {2},
number = {2},
month = {December},
issn = {2322-5483},
pages = {1--10},
numpages = {9},
keywords = {Analog to digital converter; asynchronous
process; power efficiency; asynchronous clock generator
circuit; low power designs.},
}
%0 Journal Article
%T A 5.3-9.3 fJ/Conversion-Step 4-32 MS/s 10 bit Asynchronous SAR ADC with Optimized DAC Timing Strategy in 0.13 μm CMOS
%A Dashtbayazi, Mohsen
%A Taherzadeh-Sani, Mohammad
%A Babayan, Samaneh
%A Rahiminejad, Ehsan
%J Journal of Electrical Systems and Signals
%@ 2322-5483
%D 2014
