The continuous time linear equalizer (CTLE) which compensates for the high frequency loss of electrical channels is one of the key components in the design of digital serializer / desrializer (SerDes) circuits. A new technique is described to improve the CTLE performance without any area or power overhead. This technique utilizes the bulk pin of transistors as a second gate. The proposed CTLE is designed and simulated in 130 nm CMOS technology. Post-layout simulation results demonstrate that the proposed technique can improve the eye opening of the conventional CTLE by approximately 68% at 10-Gb/s. The proposed CTLE compensates for the 12 dB loss of a 12 inches backplane at 10-Gb/s. The power consumption is only of 4.1 mW and 2 mW for a 1.2 V and 0.7 V power supply, respectively.

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