This paper presents a mixed-signal hybrid CMOS/Nano circuit to implement a fully programmable fuzzy processor that performs the zero-order Sugeno's algorithm. The programmability is incorporated in both the rule base and the membership function generator. Membership functions are stored in a memristor-based crossbar array, whereas digital memory is utilized to form a rule base. Each linguistic value whose shape can be independently chosen is stored in each row of the crossbar. Moreover, the adjacent linguistic values can have any order of overlapping ratio. Consequently, a very powerful and flexible fuzzifier is designed. The analog signal processing blocks are designed in both current and voltage mode to simplify the circuit complexity while the digital circuitry is utilized to add programmability to the whole processor. A fuzzy logic controller with nine rules, two inputs, and one output was successfully simulated using HSPICE with 350 nm technology. Simulation results confirm the proper operation of the processor that can operate up to 10 MFLIPS (Mega Fuzzy Logic Inference Per Seconds) while consuming 3.49 mW (@vdd 3.3v). Furthermore, simulation results show that an equivalent precision of 6-bits is achieved in the output signal generation. The circuit is laid out and it takes an area of approximately 0.614 mm2.

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