As the transistor sizes shrunk in advanced VLSI circuits recently, their susceptibility to the transient faults significantly has been increased which makes the reliability analysis of logic circuits more important. However, the reliability analysis of logic circuits is high computational complexity, because of multiple simultaneous errors, propagating the errors, masking mechanisms, re-convergent paths, etc. This figure becomes even more complicated in sequential circuits due to the feedback loops, where errors may store in flip-flops and re-enter the circuit. Moreover, it is essential to consider the waveform of errors in sequential circuits into account, which makes it more complex. This paper proposes a fast and scalable approach using probabilistic signal flow graphs to analyze the reliability of sequential logic circuits in the presence of multiple event transients. The proposed approach is based on nonlinear probabilistic graphs to find the probability of error for each gate after passing the circuit for an infinite number of clock cycles. Also, the proposed approach introduces a probability distribution function model to propagate the waveform of errors in the circuit to consider all masking mechanisms. Also, the proposed approach benefits from scalable runtime and memory requirements. Based on the simulation results, the proposed approach exhibits the computational complexity of .

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