Title : ( 1bit subthreshold full adders in 65nm CMOS technology )
Authors: Farshad Moradi , Dag T. Wisland , Tuan Vu Cao , Ali Peiravi , Hamid Mahmoodi ,
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Abstract
In this paper a new full adder (FA) circuit optimized for ultra low power operation is proposed. The circuit is based on modified XOR gates operated in the subthreshold region to minimize the power consumption. Simulated results using 65nm standarad CMOS models are provided. The simulation results show a 5% - 20% for frequency ranges from 1 KHz to 20MHz and supply voltages lower than 0.3V.
Keywords
, Full adder, ultra low power, subthreshold
@inproceedings{paperid:1006511,
author = {Moradi, Farshad and Dag T. Wisland and Tuan Vu Cao and Peiravi, Ali and Hamid Mahmoodi},
title = {1bit subthreshold full adders in 65nm CMOS technology},
booktitle = {20th IEEE International Conference on Microelectronics ICM2008},
year = {2008},
location = {شارجه},
keywords = {Full adder; ultra low power; subthreshold},
}
%0 Conference Proceedings
%T 1bit subthreshold full adders in 65nm CMOS technology
%A Moradi, Farshad
%A Dag T. Wisland
%A Tuan Vu Cao
%A Peiravi, Ali
%A Hamid Mahmoodi
%J 20th IEEE International Conference on Microelectronics ICM2008
%D 2008
