As the CMOS manufacturing process scales down into the ultra deep sub-micron regime, the leakage current becomes an increasingly more imortant consideration in VLSI circuit design. In this paper, a high speed and noise immune domino logic circuit is presented which uses the property of the footer transistor to alleviate the sensitivity of the dynamic node to noise and results in improved performance. The new circuit has been added to conventional footed standard domino logic for highly improving leakage tolerance, especially at the beginning of the evaluation phase. According to simulation results obtained using the 70nm Berkeley Predictive Models [1], our proposed circuit increases the noise immunity by least 2X compared to previous circuits.

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