Dynamic logic circuits are used for high performance circuits. Wide OR gates are employed for high speed processors, DRAM, SRAM and high speed logic circuits. Dynamic logic circuits are used for their high performance, but their high noise and extensive leakage has caused some problems for these circuits. However, dynamic CMOS circuits are inherently less resistant to noise than static CMOS gates. So, for dynamic CMOS, the first improvement has to be noise tolerance for the overall reliable operation of VLSI chips designed using deep submicron process technology. In this paper, we propose a new domino logic circuit scheme to reduce subthreshold leakage current in standby mode and to improve noise immunity for wide OR gates. The conditions for our simulations are: Berkeley CMOS 70nm predictive technology for simulated results [1], 0.9V power supply and bottleneck operating temperature of . Simulation results on 8, 16, 32 and 64 inputs OR gates showed improvements from 2.116X to 15.83X compared with other conventional techniques. Furthermore, while there is an area overhead of 13% compared with 8-input FLSDL, we have achieved a decreased area of 5%, 23% and 33% compared with 16, 32, and 64-input footless standard domino logic (FLSDL) respectively.

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