In this paper, a new circuit idea for improving the noise immunity of domino logics especially for wide ones, is presented. Dynamic gates are widely used for high performance processors and are also used in full adders that are the most important part of a CPU. Leakage current is the most important issue in UDSM technologies. This issue has motivated us to present a new idea for decreasing sub-threshold leakage current in domino logic circuits, especially for deep submicron technologies. Our proposed circuit enhances the noise immunity at least by a factor of 1.93to 8.4 compared with other conventional domino circuits. We have simulated our proposed circuit using the Berkeley Predictive Models (BPTM) for 70nm CMOS technology.

Keywords