Title : ( New Subthreshold Concepts in 65nm CMOS Technology )
Authors: Farshad Moradi , Dag t. Wisland , Hamid Mahmoodi , Ali Peiravi , Snorre Aunet , Tuan Vu Cao ,
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Abstract
In this paper challenges observed in 65nm technology for circuits utilizing subthreshold region operation are presented. Different circuits are analyzed and simulated for ultra low supply voltages to find the best topology for subthreshold operation. To support the theoretical discussions different topologies are analyzed and simulated. Various aspects of flip-flop circuits are described in detail to study which topology would be most suitable for ultra low supply voltage and low-power applications. Simulation results show that the power consumption decreases by at least 23% compared with other flip-flops. Also, the setup time and the hold time are improved.
Keywords
, Low-voltage, low-power, subthreshold, nanoscale
@inproceedings{paperid:1010648,
author = {Moradi, Farshad and Dag T. Wisland and Hamid Mahmoodi and Peiravi, Ali and Snorre Aunet and Tuan Vu Cao},
title = {New Subthreshold Concepts in 65nm CMOS Technology},
booktitle = {10th International Symposium on Quality Electronic Design},
year = {2009},
location = {San Jose-California, USA},
keywords = {Low-voltage; low-power; subthreshold; nanoscale},
}
%0 Conference Proceedings
%T New Subthreshold Concepts in 65nm CMOS Technology
%A Moradi, Farshad
%A Dag T. Wisland
%A Hamid Mahmoodi
%A Peiravi, Ali
%A Snorre Aunet
%A Tuan Vu Cao
%J 10th International Symposium on Quality Electronic Design
%D 2009
