A 9-bit ultra low-power successive approximation analog-to-digital converter (SA-ADC), which is able to operate at very low supply voltage, is presented. The low power consumption is achieved by using new switched-comparator architecture. In the proposed architecture the comparator, which is one of the most power hungry blocks of the SA-ADC, is switched off after the decision-making interval as well as during reset time to save power. The SA-ADC is simulated in the 0.18µm CMOS technology and the simulation results are provided. The switched-comparator SA-ADC consumes 412nW at 0.5V and as a result of the proposed switching scheme a power saving of 17.4% is obtained. It provides a signal-to-noise-and-distortion ratio (SNDR) of 50.36dB at the sampling rate of 12.5kS/s.

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