Graph partitioning techniques have been widely applied in many fields in Electrical Engineering such as VLSI design, parallel processing, circuit and layout design, power system transient stability studies, intentional islanding, optimal load flow, fault estimation, dynamic security assessment, etc. The approach to the solution of each problem may be different. The objective functions in the various potential applications of graph partitioning in electrical engineering applications are also different requiring slightly different approaches to their solution. In this paper, a review of the applications of graph partitioning to electrical engineering is presented. A new approach to power system islanding is proposed using Gaussian surfaces for aggregating groups of slow coherency generators in the multilevel kernel k-means approach to partitioning in order to further speed up the calculations. Results of the application of this approach to the IEEE 30 bus power system are illustrated as a case study example.

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