Title : ( Low-Power Adder Design for Nano-Scale CMOS )
Authors: , Seyed Saied Hosseini Khayat ,
Full TextAbstract
A fast low-power 1-bit full adder circuit suitable for nano-scale CMOS implementation is presented. Out of the three modules in a common full-adder circuit, we have replaced one with a new design, and optimized another one, all with the goal to reduce the static power consumption. The design has been simulated and evaluated using the 65 nm PTM models.
Keywords
, Nano-Scale CMOS Technology, Static Power Consumption, Adder Subcomponents.
@article{paperid:1014000,
author = {, and Hosseini Khayat, Seyed Saied},
title = {Low-Power Adder Design for Nano-Scale CMOS},
journal = {Iranian Journal of Electrical and Electronic Engineering},
year = {2009},
volume = {5},
number = {3},
month = {September},
issn = {1735-2827},
pages = {180--184},
numpages = {4},
keywords = {Nano-Scale CMOS Technology; Static Power Consumption; Adder
Subcomponents.},
}
%0 Journal Article
%T Low-Power Adder Design for Nano-Scale CMOS
%A ,
%A Hosseini Khayat, Seyed Saied
%J Iranian Journal of Electrical and Electronic Engineering
%@ 1735-2827
%D 2009
