This paper presents a modified structure and a new switching algorithm in successive-approximation analog-to-digital converters to reduce the power consumption. This technique is more efficient in applications where the input signal activity is low most of the time such as biomedical signals. For slow-varying samples, only the least significant bits of the new analog sample are extracted leading to power saving in both the capacitor-based DAC and the comparator. For an Electrocardiogram signal and with the proposed structure, the simulated power consumption of the DAC, the comparator and the entire ADC for an 8-bit 1-kS/s converter are 75%, 43% and 50% smaller than those of a conventional architecture, respectively.

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