In this paper a low-voltage low-dropout (LDO) regulator is presented in which the power supply rejection (PSR) is increased by properly driving the bulk of the PMOS pass transistor. A signal proportional to the supply noise is injected to the bulk of the PMOS transistor so that the impact of supply noise on the output voltage coming from other paths is cancelled. Using this technique the PSR of the regulator is increased by approximately 20 dB over a wide frequency range. The supply voltage of the prototype regulator is 1.2 V and the output voltage is IV. It is designed in 0.18/-lm CMOS technology and provides a current of 50 rnA to the load.

Keywords