IEEE Transactions on Power Electronics, ( ISI ), Volume (28), No (11), Year (2013-1) , Pages (4985-4997)

Title : ( Advantages and challenges of a Type-3 PLL )

Authors: Saeed Golestan , Mohammad Monfared , Francisco D. Freijedo , Josep M. Guerrero ,

Citation: BibTeX | EndNote

A phase-clocked loop (PLL) is a closed-loop feedback control system which synchronizes its output signal in frequency as well as in phase with an input signal. The phase detector, the loop filter, and the voltage controlled oscillator are the key parts of almost all PLLs. Within the areas of power electronics and power systems, which are focused on in this paper, the PLLs typically employ a proportional-integral controller as the loop filter, resulting in a type-2 control system (a control system of type-N has N poles at the origin in its open-loop transfer function). Recently, some attempts have been made to design type-3 PLLs, either by employing a specific second-order controller as the loop filter, or by implementing two parallel tracking paths for the PLL. For this type of PLLs, however, the advantages and limitations are not clear at all, as the results reported in different literature are contradictory, and there is no detailed knowledge about their stability and dynamic characteristics. In this paper, different approaches to realize a type-3 PLL are examined first. Then, a detailed study of dynamics and analysis of stability, followed by comprehensive parameters design guidelines for a typical type-3 PLL are presented. Finally, to get insight into the advantages/limitations of this type of PLLs, the performance of a well-tuned type-3 PLL is compared with a conventional synchronous reference frame PLL (which is a type-2 PLL) through extensive experimental results and some theoretical discussions.

Keywords

, Phase-locked loop (PLL) , synchronization , synchronous reference frame PLL (SRF-PLL) , type- 3
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@article{paperid:1032605,
author = {Saeed Golestan and Monfared, Mohammad and Francisco D. Freijedo and Josep M. Guerrero},
title = {Advantages and challenges of a Type-3 PLL},
journal = {IEEE Transactions on Power Electronics},
year = {2013},
volume = {28},
number = {11},
month = {January},
issn = {0885-8993},
pages = {4985--4997},
numpages = {12},
keywords = {Phase-locked loop (PLL) ; synchronization ; synchronous reference frame PLL (SRF-PLL) ; type- 3 systems},
}

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%0 Journal Article
%T Advantages and challenges of a Type-3 PLL
%A Saeed Golestan
%A Monfared, Mohammad
%A Francisco D. Freijedo
%A Josep M. Guerrero
%J IEEE Transactions on Power Electronics
%@ 0885-8993
%D 2013

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