Title : ( An Ultra-low Power Redundant Split-DAC SA-ADC using Power-optimized Programmable Comparator )
Authors: Amir Arian , Seyed Saied Hosseini Khayat ,
Full TextAbstract
An ultra-low power successive approximation(SA) analog-to-digital converter (ADC) based on the redundant search algorithm is proposed. The power consumption of thecomparator is significantly reduced through gain control of the preamplifier during conversion phase. The number of analog sampling switches is reduced to one by introducing modified clock boosting switch. A single-ended 8-bit SA-ADC is designed in a 0.18 μm CMOS process. Our simulation results show that at a supply voltage of 0.9 V and an output rate of 500 kS/s, the SAADC achieves a peak signal-to-noise-and-distortion (SNDR) ratio of 48 dB, and a power consumption of 1.63 μW, resulting in a figure of merit of 15.9 fJ/conversion-step.
Keywords
, Intergrated Circuit, Ultra-low Power, Analog to Digital Converter
@inproceedings{paperid:1033069,
author = {Arian, Amir and Hosseini Khayat, Seyed Saied},
title = {An Ultra-low Power Redundant Split-DAC SA-ADC using Power-optimized Programmable Comparator},
booktitle = {IEEE 10th International New Circuits and Systems Conference (NEWCAS), 2012},
year = {2012},
location = {Montreal},
keywords = {Intergrated Circuit; Ultra-low Power; Analog to Digital Converter},
}
%0 Conference Proceedings
%T An Ultra-low Power Redundant Split-DAC SA-ADC using Power-optimized Programmable Comparator
%A Arian, Amir
%A Hosseini Khayat, Seyed Saied
%J IEEE 10th International New Circuits and Systems Conference (NEWCAS), 2012
%D 2012
