Title : ( A New Design Technique for Low Power Subthreshold Logic Circuits with Enhanced Robustness Against Process Variations )
Authors: Seyedeh Sareh Majidi Ivari , Mohammad Maymandi Nejad ,
Full TextAbstract
Abstract— Designing logic circuits in the subthreshold regime is one of the most effective ways to reduce the power consumption of digital circuits. In the subthreshold region, the current is an exponential function of the threshold voltage and the behavior of transistors is more susceptible to process variations. In this paper, we present a new design technique that helps reduce the impact of process variations on the circuit. The proposed technique is implemented on the staticC2MOS flip-flop and the flip flop is used in a shift register. The circuit is simulated in the 90nm CMOS technology using a 0.2V supply voltage. Simulation results show that the robustness of the circuit is improved while the power consumption and the area are kept at minimum.
Keywords
, Digital circuit, CMOS, Sub-threshold, robustness, low power
@inproceedings{paperid:1035639,
author = {Majidi Ivari, Seyedeh Sareh and Maymandi Nejad, Mohammad},
title = {A New Design Technique for Low Power Subthreshold Logic Circuits with Enhanced Robustness Against Process Variations},
booktitle = {بیست و یکمین کنفرانس مهندسی برق ایران},
year = {2013},
location = {مشهد, IRAN},
keywords = {Digital circuit; CMOS; Sub-threshold; robustness; low power},
}
%0 Conference Proceedings
%T A New Design Technique for Low Power Subthreshold Logic Circuits with Enhanced Robustness Against Process Variations
%A Majidi Ivari, Seyedeh Sareh
%A Maymandi Nejad, Mohammad
%J بیست و یکمین کنفرانس مهندسی برق ایران
%D 2013
