In this paper, FinFET devices are compared to bulk CMOS technology by looking at the characteristics of both devices and their challenges in nano-scale regimes. The effects of process variations on these devices along with the effect of device parameters on their characteristics are explored. Both FinFET and CMOS devices are used in 6T and 8T-SRAM cells. Simulation results show significant improvements for FinFETbased SRAMs compared to bulk CMOS-based SRAM cells. FinFET based 6T-SRAM cell shows 39% improvement in read static noise margin, 54% higher write margin, 54% smaller minimum supply voltage applicable, and 7.3X less leakage power compared to its CMOS counterpart. 8T-SRAM using FinFET improved read static noise margin, write margin, minimum supply voltage and leakage power consumption by 7%, 64%, 50%, and 3.1X compared to bulk-CMOS 8T-SRAM, respectively.

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