Integration, the VLSI Journal, ( ISI ), Volume (50), Year (2015-1) , Pages (16-27)

Title : ( A New Write Assist Technique for SRAM Design in 65nm CMOS Technology )

Authors: HOOMAN FARKHANI , Ali Peiravi , Farshad Moradi ,

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in this paper, a new write assist technique for SRAM arrays is proposed. In this technique, to improve the write features of the SRAM cell, a negative voltage is applied to one of the bitlines in the SRAM cell while another bitline is connected to a boosted voltage. Improved write features are attributed to the boosting scheme from both sides of the SRAM cell. This technique is applied to a 10T-SRAM cell with transmission-gate access devices. The proposed design gives 2.7 * ,2.1 * faster write time, 82% and 18% improvement in write margin compared with the standard 8T-SRAM cell with and without write assist, respectively. All simulations have been done in TSMC 65 nm CMOS technology. The proposed write assist technique enables 10T-SRAM cell to operate with 24% lower supply voltage compared with standard 8T-SRAM cell with negative bitline write assist. Due to the improved supply voltage scalability a 33% leakage power reduction is achieved.

Keywords

, SRAM, Writem argin, Read static noise margin, Write
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@article{paperid:1046754,
author = {FARKHANI, HOOMAN and Peiravi, Ali and Farshad Moradi},
title = {A New Write Assist Technique for SRAM Design in 65nm CMOS Technology},
journal = {Integration, the VLSI Journal},
year = {2015},
volume = {50},
month = {January},
issn = {0167-9260},
pages = {16--27},
numpages = {11},
keywords = {SRAM، Writem argin، Read static noise margin، Write assist},
}

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%0 Journal Article
%T A New Write Assist Technique for SRAM Design in 65nm CMOS Technology
%A FARKHANI, HOOMAN
%A Peiravi, Ali
%A Farshad Moradi
%J Integration, the VLSI Journal
%@ 0167-9260
%D 2015

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