Microelectronics Reliability, ( ISI ), Volume (55), No (1), Year (2015-1) , Pages (264-271)

Title : ( node to node error sensitivity analysis usimg a graph based approach for vlsi logic circuits )

Authors: vahid hamiyati vaghef , Ali Peiravi ,

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Shrinking the transistors size and supply voltage in the advanced VLSI logic circuits, significantly increases the susceptibility of the circuits to soft errors. Therefore, analysis of the effects on other nodes, caused by the soft errors occurring at each individual node is an essential step for VLSI logic circuit design. In this paper, a novel approach based on the Mason’s gain formula, for the node-to-node sensitivity analysis of logic circuits is proposed. Taking advantage of matrix sparsity, the runtime and the memory requirement of the proposed approach become scalable. Also, taking the effects of reconvergent paths into account, the accuracy of the proposed approach is improved considerably. According to the simulation results, the proposed approach runs 4.7× faster than those proposed in the prior works while its computational complexity is O(N1.07) on the average.

Keywords

, Soft error rate; Node, to, node sensitivity analysis; Mason’s gain formula; Matrix sparsity; Combinational
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@article{paperid:1047628,
author = {Hamiyati Vaghef, Vahid and Peiravi, Ali},
title = {node to node error sensitivity analysis usimg a graph based approach for vlsi logic circuits},
journal = {Microelectronics Reliability},
year = {2015},
volume = {55},
number = {1},
month = {January},
issn = {0026-2714},
pages = {264--271},
numpages = {7},
keywords = {Soft error rate; Node-to-node sensitivity analysis; Mason’s gain formula; Matrix sparsity; Combinational logic},
}

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%0 Journal Article
%T node to node error sensitivity analysis usimg a graph based approach for vlsi logic circuits
%A Hamiyati Vaghef, Vahid
%A Peiravi, Ali
%J Microelectronics Reliability
%@ 0026-2714
%D 2015

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