IEEE Transactions on Very Large Scale Integration (VLSI) Systems, ( ISI ), Volume (24), No (40), Year (2016-3) , Pages (1593-1597)

Title : ( Low Energy Write Operation for 1T-1MTJ STT-RAM Bitcells with Negative Bitline Technique )

Authors: HOOMAN FARKHANI , Ali Peiravi , Farshad Moradi ,

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In this brief, a new write assist technique is proposed to improve the write characteristics of 1T-1MTJ STT-RAM bitcell through a symmetric write operation. This is done by applying a negative voltage to the bitline during write ‘1’ operation. The proposed technique is compared with the best previously proposed techniques. The simulation results using 65nm CMOS technology show that the proposed write assist technique results in 19% improvement in write energy compared to the boosted wordline technique. In addition, the proposed write assist technique leads to 12% and 48% bitcell area reduction compared with boosted wordline and balanced write techniques, respectively. Furthermore, the maximum voltage across the MTJ is reduced by 20% and 6% compared with boosted wordline and balanced write techniques, respectively.

Keywords

, STT-RAM, MTJ, symmetric write,
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@article{paperid:1052569,
author = {FARKHANI, HOOMAN and Peiravi, Ali and Farshad Moradi},
title = {Low Energy Write Operation for 1T-1MTJ STT-RAM Bitcells with Negative Bitline Technique},
journal = {IEEE Transactions on Very Large Scale Integration (VLSI) Systems},
year = {2016},
volume = {24},
number = {40},
month = {March},
issn = {1063-8210},
pages = {1593--1597},
numpages = {4},
keywords = {STT-RAM; MTJ; symmetric write; CMOS},
}

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%0 Journal Article
%T Low Energy Write Operation for 1T-1MTJ STT-RAM Bitcells with Negative Bitline Technique
%A FARKHANI, HOOMAN
%A Peiravi, Ali
%A Farshad Moradi
%J IEEE Transactions on Very Large Scale Integration (VLSI) Systems
%@ 1063-8210
%D 2016

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