Spin-transfer torque random access memory (STT-RAM) has emerged as an attractive candidate for future non-volatile memories. However, the write operation in 1T-1MTJ STT-RAM bit-cells is asymmetric and stochastic which leads to high energy consumption and long latency. In this paper, a new write assist technique is proposed to terminate the write operation immediately after switching takes place in the MTJ. As a result, both write time and write power of 1T-1MTJ bit-cells improve. Moreover, the proposed write assist technique is robust in the presence of process variations. Simulation results using 65nm CMOS access transistor and 40-nm magnetic tunneling junction technology confirm that the proposed write assist technique results in three orders of magnitude improvement in bit error rate compared with the best existing techniques. Moreover, the proposed write assist technique leads to 81% power savings compared with a cell without write assist.

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