This paper presents a low-power robust static random access memory (SRAM) using a novel quasi-Schottky-barrier ultrathin body and ultrathin buried oxide (UTBB) silicon-on-insulator (SOI) device. In the proposed device, the drain terminal is highly doped and a metallic source terminal is used. Given the proposed structure, asymmetric characteristicswill be achieved according to the drain–source bias voltage (VDS). These characteristics of the proposed device are extensively analyzed and compared with a conventional symmetric UTBB SOI device. The asymmetry nature of the proposed device will lead to the mitigated read–write conflict of the 6T-SRAM cell. The simulation results show a leakage reduction of 18% at VDD = 1 V in comparison with the 6T-SRAM cell realized by conventional symmetric UTBB SOI device. Furthermore, in comparison with the conventional 6T-SRAM, the realized cell shows a 54% improvement in read static noise margin, 6.6% higher write margin, and 3.1× faster write at the cost of a longer access time. To achieve a practical read access time, we utilize split bitline approach.

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