In this paper, a 6-bit 100-MS/s fully-digital time-based analog-to-digital converter (T-ADC) is proposed. The proposed structure uses a new bulk-driven structure for the required delay element circuits that not only presents a highly-linear voltage-to-delay characteristic, but also reduces the power consumption of the converter. Moreover, the proposed structure utilizes a new switching technique to reduce the complexity of the circuit. In addition, since the output latches of the converter are removed in the proposed T-ADC, the power consumption and the occupied area of the proposed circuit are reduced compared with the conventional structure. The proposed fully-digital T-ADC has been designed and implemented in a 0.13-μm CMOS process with a supply voltage of 1.2 V. Post-layout simulation results show that the proposed ADC archives an effective number of bits (ENOB) of 5.22 bits at the cost of 380 μW power consumption. The silicon area occupied by the proposed circuit is 200 μm×45 μm that is reduced by 75% compared with the conventional counterpart.

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