This paper proposes a new low-power time-todigital converter (TDC). In contrast to the previous works that digitize each new input sample independent of the previous ones, the proposed structure obtains the digital code of the new sample based on the difference between the previous sample and the new one. Therefore, since the activity of the circuit is reduced, its power consumption is saved, especially for the applications that the variation of the input signal is usually much smaller than the signal range, such as sensor interface circuits. Based on the proposed structure, a 200 kS/s TDC circuit with a resolution of 3.2 ps is designed and simulated in a 65-nm CMOS technology. Post-layout simulation results show that the proposed structure achieves an effective number of bits (ENOB) of 7.52 bits at the cost of 10.1 μW power consumption. Moreover, the effective area occupied by the circuit is 110 μm x 130 μm.

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