his paper proposes a power-efficient voltage level shifter architecture that is able to operate in the sub-threshold region. To avoid the static power dissipation, the proposed structure employs an auxiliary circuit to charge the internal nodes up to VDDH. Moreover, the strength of the pull-down devices are increased with the aid of a second auxiliary circuit. Post-layout simulation results of the proposed structure in a 0.18-μm CMOS technology show that at the input low supply voltage of VDDL=0.3 V and the high supply voltage of VDDH=1.8 V, the level shifter presents a propagation delay of 46 ns, a static power dissipation of 230 pW, and an energy per transition of 84 fJ, when the frequency of the input signal is 1 MHz.

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