This paper presents a new low-power and high-precision digital winner-take-all (WTA) circuit. The proposed circuit employs a parallel architecture with a symmetric positive-feedback network to determine the maximum (winner) input signal. The feedback network not only improves the circuit’s speed and precision, but also ensures a unique winner is determined, even when the input signals are very close together. Furthermore, the proposed symmetric structure avoids the systematic error present in previous designs, leading to a further improvement in precision. The proposed WTA circuit has been designed and simulated in a standard 180-nm CMOS technology. Post-layout simulations show that the three-input circuit achieves a precision of 99.96% under a 0.5 V supply voltage and at an operating frequency of 1 MHz. The circuit consumes a power of 32.4 nW and occupies an area of 23.6 μm× 12.6 μm.

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