With the rapid scaling down of CMOS manufacturing technology, the reduction in leakage power has become an important concern in low voltage, low power and high performance applications. In this paper a novel circuit design technique is presented which minimizes sub-threshold leakage current by zeroing drain-source voltage. This results in a reduction of leakage power consumption in sleep mode especially in wide gates. Since leakage power due to sub-threshold current in sub-100nm technologies increases dramatically the proposed circuit design technique is designed to be less dependent on technology scale and temperature. Since there is no additional circuitry needed for power reduction in this circuit design technique, there is no additional circuitry needed for power reduction. Thus, circuit complexity and dies area cost is much less than existing logic families. Moreover, the switching time between sleep mode and active mode is shorter.

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