Successive-approximation analog-to-digital converters (SA-ADCs) have recently been widely used for moderate-speed moderate-resolution applications where power consumption is of major concern. In this paper, several techniques are proposed to further reduce the power consumption of an SA-ADC. These solutions include a splitsegmented architecture for the capacitor-based digital-to-analog converter (DAC), a modified switching scheme for the DAC, and employing a smaller supply voltage for the comparator and the successive-approximation register while using a new powerefficient digital level converter. Spectre simulation results of a single-ended 10-bit 100kS/s SA-ADC in a 0.13-µm CMOS technology employing the proposed techniques show that the ADC (excluding reference buffers) consumes less than 1 µW of power while offering an effective number of bits of 9.2.

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