Settling performance of operational amplifiers (opamps) is of great importance in analog signal-processing applications. Among different architectures, three-stage amplifiers are gaining more attention between analog circuit designers of modern technologies with small supply voltages where few devices can be stacked. Previous attempts to design and optimize a three-stage opamp based on settling time suffer from lack of a comprehensive analysis of the settling behavior and closed-form relationships between settling time/error and other parameters. In this paper, a thorough analysis of the settling response of three-stage nested-Miller-compensated opamps, including linear and non-linear sections, is presented. Based on this analysis, a design methodology is presented which determines the circuit requirements to achieve a desired settling time/error. It allows optimizations in power consumption and area based on settling time.

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