Title : ( A new asymmetric 6T SRAM cell with a write assist technique in 65 nm CMOS technology )
Authors: HOOMAN FARKHANI , Ali Peiravi , fARSHAD MORADI ,
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Abstract
A newasymmetric6T-SRAMcelldesignispresentedforlow-voltagelow-poweroperationunderprocess variations.Thewritemarginoftheproposedcellisimprovedbytheuseofanewwrite-assisttechnique. Simulation resultsin65nmtechnologyshowthattheproposedcellachievesthesameRSNMasthe asymmetric 5T-SRAMcelland77%higherRSNMthanthestandard6T-SRAMcellwhileitisableto perform writeoperationwithoutanywriteassistat VDD¼1 V.MonteCarlosimulationsforan8KbSRAM (25632) arrayindicatethatthescalabilityofoperatingsupplyvoltageoftheproposedcellcanbe improvedby10%and21%comparedtoasymmetric5T-andstandard6T-SRAMcells;21%and53%lower leakage powerconsumption,respectively.Theproposed6T-SRAMcelldesignachieves9%and19%lower cell areaoverheadcomparedwithasymmetric5T-andstandard6T-SRAMcells,respectively.Considering the areaoverheadforthewriteassist,replicacolumnandthereplicacolumndriverof2.6%,theoverall area reductionindieareais6.3%and16.3%ascomparedwitharraydesignswithasymmetric5T-and standard 6T-SRAMcells.
Keywords
, SRAM, Write Margin, ReadStaticNoiseMargin, CMOS
@article{paperid:1045836,
author = {FARKHANI, HOOMAN and Peiravi, Ali and FARSHAD MORADI},
title = {A new asymmetric 6T SRAM cell with a write assist technique in 65 nm CMOS technology},
journal = {Microelectronics Journal},
year = {2014},
volume = {45},
number = {11},
month = {December},
issn = {1879-2391},
pages = {1556--1565},
numpages = {9},
keywords = {SRAM; Write Margin; ReadStaticNoiseMargin; CMOS},
}
%0 Journal Article
%T A new asymmetric 6T SRAM cell with a write assist technique in 65 nm CMOS technology
%A FARKHANI, HOOMAN
%A Peiravi, Ali
%A FARSHAD MORADI
%J Microelectronics Journal
%@ 1879-2391
%D 2014
