Title : ( A Low-Power Level-Shifting Architecture for Sub-threshold Logic Circuits )
Authors: Mehdi Saberi , Seyed Rasool Hosseini , Reza Lotfi ,Access to full-text not allowed by authors
Abstract
This paper presents a power-efficient voltage level shifter converting low levels of input voltages (sub-threshold) to high levels of the output voltages (above threshold). In order to reduce the existing contention in the output nodes between pull-up and pull-down devices, the proposed circuit uses a current generator to reduce the strength of the pull-up device when the pull-down device is pulling down the output node. This causes the circuit to be functional even for the sub-threshold input voltages. In order to avoid the static power dissipation, this current generator turns on only during the transition times in which the logic level of the input signal is not corresponding to the output logic level. Simulation results of the proposed circuit in a 0.18-µm technology confirm that for a low supply voltage of VDDL=0.42V at the input and a high supply voltage of VDDH=1.8V at the output, the level shifter has a propagation delay of 22ns, an energy per transition of 340fJ, and a static power dissipation of 0.42nW for 1-MHz input signal.
Keywords
, Level shifter, level converter, sub-threshold, low power operation, dual supply.@article{paperid:1053510,
author = {Saberi, Mehdi and Hosseini, Seyed Rasool and Lotfi, Reza},
title = {A Low-Power Level-Shifting Architecture for Sub-threshold Logic Circuits},
journal = {Journal of Electrical Systems and Signals},
year = {2016},
volume = {2},
number = {2},
month = {March},
issn = {2322-5483},
pages = {11--16},
numpages = {5},
keywords = {Level shifter; level converter; sub-threshold; low power operation; dual supply.},
}
%0 Journal Article
%T A Low-Power Level-Shifting Architecture for Sub-threshold Logic Circuits
%A Saberi, Mehdi
%A Hosseini, Seyed Rasool
%A Lotfi, Reza
%J Journal of Electrical Systems and Signals
%@ 2322-5483
%D 2016