Spin-transfer torque random-access memory (STT-RAM) is a nonvolatile, scalable, and fast memory structure, which benefits from high endurance and relatively low power consumption. However, there are some challenges in designing STT-RAM such as the tradeoff between decreasing the write current and the retention time. Increasing the write voltage as the cell size is scaled down is another challenge for STT-RAM due to the increasing resistance of its magnetic tunnel junction (MTJ). In this paper, a novel STT-RAM cell structure with a graphene-based spin filter including three graphene layers as MTJ is proposed for sub-20 nm technology nodes (e.g., 14 nm and beyond). By flowing a small (e.g., 3 μA) and short width current pulse (e.g., 1 ns) through the center graphene layer, a reduction of 69% in the amplitude of the intrinsic switching current density (38% less than the predicted value for the conventional in-plane STT-RAM) is achieved without any penalty of data retention time for an 8 nm technology node. Furthermore, by flowing current through the center graphene layer, the intrinsic switching voltage of the proposed structure is decreased by 27%, 51%, and 59% for 14, 10, and 8 nm widths of the MTJ, respectively. The behavior of the proposed structure in a fast (precessional) switching mode (switching time less than 3 ns) is evaluated. Consequently, a reduction of 38% in the switching current density and the switching voltage can be attained for the 8 nm technology node, using the proposed idea. Simulation results are obtained using an object-oriented micromagnetic framework.

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