In this paper, a silicon–on–insulator (SOI) p–n–p–n tunneling field–effect transistor (TFET) with a silicon doped hafnium oxide (Si:HfO2) ferroelectric gate stack is proposed and investigated via 2D device simulation with a calibrated nonlocal band–to–band tunneling model. Utilization of Si:HfO2 instead of conventional perovskite ferroelectrics such as lead zirconium titanate (PbZrTiO3) and strontium bismuth tantalate (SrBi2Ta2O9) provides compatibility to the CMOS process as well as improved device scalability. By using Si:HfO2 ferroelectric gate stack, the applied gate voltage is effectively amplified that causes increased electric field at the tunneling junction and reduced tunneling barrier width. Compared with the conventional p–n–p–n SOI TFET, the on–state current and switching state current ratio are appreciably increased; and the average subthreshold slope (SS) is effectively reduced. The simulation results of Si:HfO2 ferroelectric p–n–p–n SOI TFET show significant improvement in transconductance (9.8X enhancement) at high overdrive voltage and average subthreshold slope (35% enhancement over nine decades of drain current) at room temperature, indicating that this device is a promising candidate to strengthen the performance of p–n–p–n and conventional TFET for a switching performance.

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