In this paper, a novel low-voltage time-domain fully-digital winner-take-all (WTA) circuit is proposed. In order to enhance the accuracy and the speed of the circuit, the proposed structure amplifies the delay time difference created by the input signals, and then employs a positive-feedback loop, similar to the voltage-mode counterpart, to detect the first delayed pulse corresponding to the winner signal uniquely. Furthermore, the circuit is able to operate correctly for small values of the supply voltage even down to sub-threshold levels, leading to low power consumption. Based on the proposed structure, a 3-input WTA circuit has been designed and fabricated in a 0.13-μm CMOS technology with a 0.5-V supply voltage. The measurement results show that the circuit consumes 0.75 μW at 1 MHz clock frequency for a 2-mV resolution. The silicon area of the proposed circuit is 24μm×35μm.

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