The downsizing of nanoscale circuits imposes new challenges for circuit reliability, including hard defects, soft errors and unsaturated voltage/current. Many studies on the reliability of digital circuits have focused on achieving accurate reliability estimation and more effiiency for larger circuits. To achieve accurate reliability estimation, it is necessary to address the issue of error propagation and consider correlated signals from reconverging paths in reliability calculations. In this paper, an error propagation probability model for each gate, which takes into account the probability of an unreliable logic gate’s input signal and relates it to the probability of the output signal is proposed. Additionally, we introduce an effiient approach that utilizes a new fanout matrix to tackle the reconvergent fanouts problem. Furthermore, to ensure an accurate estimation of combinational logic circuit reliability, the probabilities obtained for each fanout should be included in the calculations by defiing a fanout probability matrix. To address this issue, a new method is proposed at each calculation stage, aiming to minimize computational complexity making it suitable for large circuits with a signifiant number of fanouts. We conducted various simulations to demonstrate the accuracy and scalability of the proposed method on the ISCAS 85 benchmark circuit and EPFL Benchmark. The results show less than 1% average relative error in reliability estimation and outperform state-of-the-art methods in reliability estimation and algorithm runtime.

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