A new switching algorithm is proposed in Successive Approximation Analog-to-Digital Converters (SA-ADCs) to reduce the power consumption in both DAC and comparator. This technique is more efficient in applications where the input signal has low-varying characteristics. For slow-varying samples, only the least significant bits of the new analog sample are extracted leading to power saving in both the capacitor-based DAC and the comparator. For an Electrocardiogram (ECG) signal and with the proposed structure, the simulated power consumption of the DAC, the comparator and the entire ADC for an 8-bit 10-kS/s converter are 74%, 38% and 52% less than those of a conventional architecture, respectively.

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